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datasheet eeprom programmable clock generator i dt 5 v 4 9 ee9 0 1 idt? eeprom programmable clock generator 1 idt5v49ee901 rev s 071015 description the idt5v49ee901 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. there are four internal plls, each individually programmable, allowing for four unique non-integer-related frequencies. the frequencies are generated from a single reference clock. the reference clock can come from one of the two redundant clock inputs. automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. the idt5v49ee901 is in-system, programmable and can be programmed through the use of i 2 c interface. an internal eeprom allows the user to save and restore the configuration of the device without having to reprogram it on power-up. each of the four plls has an 7-bit reference divider and a 12-bit feedback divider. this allows the user to generate four unique non-integer-related frequencies. the pll loop bandwidth is programmable to allow the user to tailor the pll response to the application. for instance, the user can tune the pll parameters to minimize jitter generation or to maximize jitter attenuation. spread spectrum generation and/or fractional divides are allowed on two of the plls. there are a total of six 8-bit output dividers. each output bank can be confi gured to support lvttl, lvpecl, lvds or hcsl logic levels. out0 (output 0) supports 3.3v single-ended output only. the outputs are connected to the plls via a switch matrix. the switch matrix allows the user to route the pll outputs to any output bank. this feature can be used to simplify and optimize the board layout. in addition, each output's slew rate and enable/disable function is programmable. features four internal plls internal non-volatile eeprom fast (400khz) mode i 2 c serial interface input frequency range: 1 mhz to 200 mhz output frequency range: 4.9 khz to 500 mhz reference crystal input with programmable linear load capacitance ? crystal frequency range: 8 mhz to 50 mhz each pll has a 7-bit reference divider and a 12-bit feedback-divider 8-bit output-divider blocks fractional division capability on one pll two of the plls support spread spectrum generation capability i/o standards: ? outputs - 3.3 v lvttl/ lvcmos ? outputs - lvpecl, lvds and hcsl ? inputs - 3.3 v lvttl/ lvcmos programmable slew rate control programmable loop bandwidth programmable output inversion to reduce bimodal jitter redundant clock inputs with auto and manual switchover options individual output enable/disable power-down mode 3.3v core v dd available in tssop and vfqfpn packages -40 to +85 c industrial temp operation
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 2 idt5v49ee901 rev s 071015 functional block diagram 1. out1 & out2, out4 & out4 , out3 & out6, and out5 & out5 pairs can be configured to be lvds, lvpecl or hcsl, or two single-ended lvttl outputs. 2. clkin, clksel, sd/oe and sel[2:0] have pull down resistors. pll0 (ss) pll1 pll2 pll3 (ss) /div4 /div2 /div1 /div3 /div6 /div5 xin/ref xout clkin clksel sda scl sel[2:0] out0 out1 out2 out4 out4 out3 out6 out5 out5 sd/oe s rc 0 s rc 1 s rc 2 s rc 4 s rc 3 s rc 6 s rc 5 control logic s1 s3
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 3 idt5v49ee901 rev s 071015 pin configuration pin descriptions 17 16 9 15 vdd 12 13 14 out3 clksel 2018 11 out1 out2 19 10 28 pin tssop (top view) 82 1 7 out4b clkin 22 out5 5 gnd sel1 2423 6 42 5 3 out6 vdd 26 1 sd/oe 2827 2 vdd gnd sclk vddx vdd sel2 gnd out5b sdat xin/ref xout out0 sel0 avdd out4 32 pin vfqfpn (top view) 16 vdd 15 out5b 11 out4b 14 out5 13 gnd 12 vdd 10 out4 9 vdd 17 gnd 18 sdat 20 clksel 21 avdd 22 gnd out6 23 24 out3 sclk 19 25 vdd sel2 26 27 sel1 28 sel0 31 gnd 30 out0 32 vdd 29 sd/oe 1 vdd 2 xout 4 vddx 3 xin/ref 5 clkin gnd 6 7 out1 out2 8 pin name pg28 pin# nl32 pin# i/o pin type pin description clkin 8 5 i lvttl input clock. weak internal pull down resistor. xout 5 2 o lvttl crystal_out -- reference crystal feedback. xin / ref 6 3 i lvttl crystal_in -- reference crystal input or external reference clock input. sdat 18 18 i/o open drain bidirectional i 2 c data. an external pull-up resistor is required. see i 2 c specification for pull-up value recommendation. sclk 19 19 i lvttl i 2 c clock. an external pull-up resistor is required. see i 2 c specification for pull-up value recommendation. clksel 20 20 i lvttl input cloc k selector. weak internal pull down resistor. sel2 26 26 i lvttl configuration select pin. weak internal pull down resistor. sel1 27 27 i lvttl configuration select pin. weak internal pull down resistor. sel0 28 28 i lvttl configuration select pin. weak internal pull down resistor. sd/oe 1 29 i lvttl enables/disables the outputs or powers down the chip. the sp bit (0x02) controls the polarity of the signal to be either active high or low. (default is active low.) weak internal pull down resistor. out0 2 30 o lvttl configurable clock output 0. out1 10 7 o adjustable 1 configurable clock output 1. single-ended or differential when combined with out2.
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 4 idt5v49ee901 rev s 071015 out2 11 8 o adjustable 1 configurable clock output 2. single-ended or differential when combined with out1. out3 24 24 o adjustable 1 configurable clock output 3. single-ended or differential when combined with out6. out4 13 10 o adjustable 1,2 configurable clock output 4. single-ended or differential when combined with out4b. out4b 14 11 o adjustable 1,2 configurable clock output 4b. single-ended or differential when combined with out4. out5 16 14 o adjustable 1,2 configurable clock output 5. single-ended or differential when combined with out5b. out5b 17 15 o adjustable 1,2 configurable clock output 5b. single-ended or differential when combined with out5. out6 23 23 o adjustable 1 configurable clock output 6. single-ended or differential when combined with out3. vdd 3, 7, 12, 25 1, 9, 12, 16, 25, 32 power device power supply. connect to 3.3v. vddx 4 4 power crystal oscillator power supply. connect to 3.3v through 5 ? resistor. use filtered analog power supply if available. avdd 21 21 power device analog power supply. connect to 3.3v. use filtered analog power supply if available. gnd 9, 15, 22 6, 13, 17, 22, 31,pad power connect to ground. 1.outputs are user programmable to drive single-ended 3.3-v lvttl, or differential lvds, lvpecl or hcsl interface levels 2. when only an individual single-ended clock output is required, tie out# and out#b together. 3. analog power plane should be isolated from a 3.3v power plane through a ferrite bead. 4. each power pin should have a dedicated 0.01f de-coupl ing capacitor. digital vdds may be tied together. 5. unused clock inputs (refin or clkin) must be pulled high or low - they cannot be left floating. if the crystal oscillator is not used, xout must be left floating. pin name pg28 pin# nl32 pin# i/o pin type pin description
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 5 idt5v49ee901 rev s 071015 pll features and descriptions pll0 block diagram pll1, pll2 and pll3 block diagram vco n d a sigma-delta modulator 12-bit 7-bit 4-bit vco n d 12-bit 7-bit pre-divider (d) 1 values multiplier (m) 2 values programmable loop bandwidth spread spectrum generation capability pll0 1 - 127 10 - 8206 yes yes pll1 1 - 127 1 - 4095 yes no pll2 1 - 127 1 - 4095 yes no pll3 3 - 127 12 - 4095 yes yes 1.for pll0, pll1 and pll2, d=0 means pll power do wn. for pll3, 0, 1, and 2 are dnu (do not use) 2.for pll0, m = 2*n + a + 1 (for a > 0); m = 2*n (for a = 0); a < n-1. for pll1, pll2 and pll3, m=n.
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 6 idt5v49ee901 rev s 071015 reference clock input pins and selection the idt5v49ee901 supports up to two clock inputs. one of the clock inputs (xin/ ref) can be driven by either an external crystal or a reference clock. the second clock input (clkin) can only be driven from an external reference clock. the clksel pin selects the input clock from either xtal/ref or clkin. either clock input can be set as the primary clock. the primary clock designation is to establish which is the main reference clock to the plls. the non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. the primsrc bit (0xbe through 0xc3) determi nes which clock input will be selected as primary clock. when primsrc bit is "0", xin/ref is selected as the primary clock, and when "1", clkin as the primary clock. the two external reference clocks can be manually selected using the clksel pin. the sm bits (0xbe through 0xc3) must be set to "0x" for manual switchover which is detailed in switchover modes section. crystal input (xin/ref) the crystal used should be a fundamental mode quartz crystal; overtone crystals should not be used. when the xin/ref pin is driven by a crystal, it is important to set the internal inverter oscillator drive strength and tuning/load capacitor values correctly to achieve the best clock performance. these values are programmable through i 2 c interface to allow for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. the internal load capacitors are true parallel-plate capacitors for ultra-linear performance. parallel-plate capacitors were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. external non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency requirements. the value of the internal load capacitors are determined by xtal[4:0] bits. the load capacitance can be set with a resolution of 0.125 pf for a total crystal load ranging from 3.5 pf to 7.5 pf. check with the crystal vendor's load capacitance specification for the exact setting to tune the internal load capacitor. the following equation governs how the total internal load capacitance is set. xtal load cap = 3.5 pf + xtal[4:0] * 0.125 pf (eq. 1) when using an external reference clock instead of a crystal on the xtal/ref pin, the input load capacitors may be completely bypassed. this allows for the input frequency to be up to 200 mhz. when using an external reference clock, the xout pin must be left floating, xtal must be programmed to the default value of ?00h?, and the crystal drive strength bit, xdrv (0x06), must be set to the default value of ?11h?. switchover modes the idt5v49ee901 features redundant clock inputs which supports both automatic and manual switchover mode. these two modes are determined by the configuration bits, sm (0xbe through 0xc3). the primary clock source can be programmed, via the primsrc bit, to be either xin/ref or clkin. the other clock input will be considered as the secondary source. no te that the switchover modes are asynchronous. if the reference clocks are directly routed to outx with no phase relationship, short pulses can be generated during switchover. the automatic switchover mode will work only when the primary clock source is xin/ref. switchover modes are not supported for crystal input configurations. manual switchover mode when sm[1:0] is "0x", the redundant inputs are in manual switchover mode. in this mo de, clksel pin is used to switch between the primary and secondary clock sources. as previously mentioned, the primary and secondary clock source setting is determined by the primsrc bit. during the switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and frequency relationship between the primary and secondary clocks. automatic switchover mode the redundant inputs are in automatic switchover mode. automatic switchover mode has revertive functionality. the input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary cloc k cycles. if both reference parameter bits step (pf) min (pf) max (pf) xtal 8 0.125 0 4
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 7 idt5v49ee901 rev s 071015 clocks are at different freque ncies, the device will always remain on the primary clock unless it is absent for two secondary clock cycles. the secondary clock must always run at a frequency less than or equal to the primary clock frequency. r eference divider, feedback divider, and output divider each pll incorporates a 7-bit reference divider (d[6:0]) and a 12-bit feedback divider (n[11:0]) that allows the user to generate four unique non-integer-related frequencies. each output divide supports 8-bit output-divider (pm and q[7:0]). the following equation governs how the output frequency is calculated. where fin is the reference frequency, m is the total feedback-divider value, d is the reference divider value, odiv is the total output-divider value, and fout is the resulting output frequency. for pll0, m = 2 * n + a + 1 (for a>0) m = 2 * n (for a = 0) for pll1, pll2 and pll3, m = n pm and q[6:0] are the bits used to program the 8-bit output-dividers for outputs out1-6. out0 does not have any output divide along its path. the 8-bit output-dividers will bypass or divide down the output banks' frequency with even integer values ranging from 2 to 256. there is the option to choose between disabling the output-divider, utilizing a div/1, a div/2, or the 7-bit q-divider by using the pm bit. if the output is disabled, it will be driven high, low or high impedance, depending on oem[1:0]. each bank, except for out0, has a pm bit. when disabled, no clocks will appear at the ou tput of the divider, but will remain powered on. the output divides selection table is shown below. note that the actual 7-bit q-divider value has a 2 added to the integer value q and the outputs are routed through another div/2 block. the output divider should never be disabled unless the output ban k will never be used during normal operation. the output frequency range for lvttl outputs are from 4.9khz to 200mhz. the output frequency for lvpecl/lvds/hcsl output s range from 4.9khz to 500mhz. spread spectrum generation (pll0) pll0 supports spread spec trum generation capability, which users have the option of turning on or off. spread spectrum profile, frequency, and spread amplitude are fully programmable. the programmable spread spectrum generation parameters are tssc[3:0], nssc[2:0], ss_offset[5:0], sd[3:0], dith, and x2 bits. these bits are in the memory address from 0xac to 0xbd for pll0. the spread spectrum generation on pll0 can be enabled/disabled using the tssc[3:0] bits. to enable spread spectrum, set tssc > '0' and set nssc[2:0], ss_offset[5:0], sd[3:0], and the a[3:0] (in the total m value) accordingly. to disable spread spectrum generation, set tssc = '0'. tssc[3:0] these bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. the modulation frequency can be calculated with the tssc bits in conjunction with the nssc bits. valid tssc integer values for the modulation frequency range from 5 to 14. values of 0 - 4 and 15 should not be used. nssc[2:0] these bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum waveform. all four quadrants of the spread spectrum waveform are mirror images of each other. the modulation frequency is also calculated based on the nssc bits in conjunction with the tssc bits. valid nssc integer f out = m d ( ) f in * odiv (eq. 1) q[6:0] pm output divider 111 1111 0 disabled 1/ 1 <111 1111 0 /2 1 /((q[6:0] + 2) * 2)
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 8 idt5v49ee901 rev s 071015 values range from 1 to 6. values of 0 and 7 should not be used. ss_offset[5:0] these bits are used to program the fractional offset with respect to the nominal m integer value. for center spread, the ss_offset is set to '0' so that the spread spectrum waveform is centered about the nominal m (mnom) value. for down spread, the ss_offset > '0' such the spread spectrum waveform is centered about the (mideal -1 +ss_offset) value. the downspread percentage can be thought of in terms of center spread. for example, a downspread of -1% can also be considered as a center spread of 0.5% but with mnom shifted down by one and offset. the ss_offset has integer values ranging from 0 to 63. sd[3:0] these bits are used to shape the profile of the spread spectrum waveform. these are delta-encoded samples of the waveform. there are twelve sets of sd samples. the nssc bits determine how many of these samples are used for the waveform. the sum of these delta-encoded samples (sigma delta- encoded samples) determine the amount of spread and should not exceed (63 - ss_offset). the maximum spread is inversely proportional to the nominal m integer value. dith this bit is used for dithering the sigma-delta-encoded samples. this will randomize the least-significan t bit of the input to the spread spectrum modulator. set the bit to '1' to enable dithering.x2 this bit will double th e total value of the sigma-delta-encoded -samples which will increase the amplitude of the spread spectrum waveform by a factor of two. when x2 is '0', the amp litude remains nominal but if set to '1', the amplitude is in creased by x2. the following equations govern how the spread spectrum is set: t ssc = tssc[3:0] + 2 (eq. 2) n ssc = nssc[2:0] * 2 (eq. 3) sd[3:0] k = s j+1 (unencoded) - s j (unencoded) (eq. 4) where s j is the unencoded sample out of a possible 12 and sd k is the delta-encoded sample out of a possible 12. amplitude = ((2*n[11:0] + a[3:0] + 1) * spread% / 100) /2 (eq. 5) if 1 < amplitude < 2, then set x2 bit to '1'. modulation frequency: f pfd = f in / d (eq. 6) f vco = f pfd * m nom (eq. 7) f ssc = f pfd / (4 * nssc * tssc) (eq. 8) spread:??? = sd 0 + sd 1 + sd 2 + ? + sd 11 the number of samples used depends on the n ssc value ??? 63 - ss_offset spread% = ( ??? * 100)/(64 * (2*n[11:0] + a[3:0] + 1) (eq. 9) max spread% / 100 = 1 / m nom or 2 / m nom (x2=1)
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 9 idt5v49ee901 rev s 071015 profile: waveform starts with ss_offset, ss_offset + sd j , ss_offset + sd j+1 , etc. spread spectrum using sinusoidal profile example f in = 25mhz, f out = 100mhz, fssc = 33khz with center spread of 2%. find the necessary spread spectrum register settings. since the spread is center, the ss_offset can be set to '0'. solve for the nominal m value; keep in mind that the nominal m should be chosen to maximize the vco. start with d = 1, using eq.6 and eq.7. m nom = 1200mhz / 25mhz = 48 using eq.4, we arbitrarily choose n = 22, a = 3. now that we have the nominal m value, we can determine tssc and nssc by using eq.8. nssc * tssc = 25mhz / (33khz * 4) = 190 however, using eq. 2 and eq.3, we find that the closest value is when tssc = 14 and nssc = 6. keep in mind to maximize the number of samples used to enhance the profile of the spread spectrum waveform. tssc = 14 + 2 = 16 nssc = 6 * 2 = 12 nssc * tssc = 192 use eq.10 to determine the value of the sigma-delta-encoded samples. 2% = ???? * 100)/(64 * 48) ??? = 61.4 either round up or down to the nearest integer value. therefore, we end up with 61 or 62 for sigma-delta-encoded samples. since the sigma-delta-encoded samples must not exceed 63 with ss_offset set to '0', 61 or 62 is well within the limits. it is the discretion of the user to define the shape of the profile that is better suited for the intended application. using eq. 9 again, the actual spread for the sigma-delta-encoded samples of 56 and 57 are 1.99% and 2.02%, respectively. use eq.10 to determine if the x2 bit needs to be set; amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1 therefore, the x2 = '0 '. the dither bit is left to the discretion of the user. the example above was of a center spread using spread spectrum. for down spread, the nominal m value can be set one integer value lower to 47. note that the idt5v49ee901 should not be programmed with tssc > '0', ss_offset = '0 ', and sd = '0' in order to prevent an unstable state in the modulator. the pll loop bandwidth must be at least 10x the modulation frequency along with higher damping (larger ? uz) to prevent the spread spectrum from being filtered and reduce extraneous noise. refer to the loop filter section for more detail on ? uz. the a[3:0] must be used for spread spectrum, even if the to tal multiplier value is an even integer.
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 10 idt5v49ee901 rev s 071015 spread spectrum generation (pll3) pll3 support spread spectrum generation capability, which users have the option of turning on and off. spread spectrum profile, frequency, and spread are fully programmable (within limits). the technique is different from that used in pll0. the programmable spread spectrum generation parameters ar e ss_d3[7:0], ssvco[15:0], ssenb, ip3[4:0] and rz3[3:0] bits. these bits are in the memory address range of 0x4c to 0x85 for pll3. the spread spectrum generation on pll3 can be enabled/disabled using th e ssenb bit. to enable spread spectrum, set ssenb = '1'. for spread enabled: spread spectrum is configured using ss_d3(spread spectrum reference divide) and ssvco (spread spectrum loop feedback counter). ss is the total spread spectrum amount (i.e. center spread + 0.5% has a total spread of 1.0% and down spread -0.5% has a total spread of 0.5%.) loop filter the loop filter for each pll can be programmed to optimize the jitter performance. the low-pass frequency response of the pll is the mechanism that dictates the jitter transfer characteristics. the loop bandwidth can be extracted from the jitter transfer. a narrow loop bandwidth is good for jitter attenuation while a wide loop band width is best for low-jitter frequency generation. the specific loop filter components that can be programmed are the resistor via the rz[3:0] bits, zero capacitor via the cz bit (for pll0, pll1 and pll2), and the charge pump current via the ip[2:0] bits (for pll0, pll1 and pll2) or ip[3:0] (for pll3). the following equations govern how the loop filter is set for pll0 - pll2: resistor (rz) = (rz[0] + 2* rz[1]+4* rz[2] + 8* rz[3])* 4.0 kohm zero capacitor (cz) = 196 pf + cz* 217 pf pole capacitor (cp) = 15 pf charge pump (ip) = 6 * (ip[0] + 2*ip[1]+4*ip[2]) ua vco gain (k vco ) = 900 mhz/v * 2 ? the following equations govern how the loop filter is set for pll3: for non-spread spectrum operation: for spread spectrum operation: zero capacitor (cz) = 250 pf pole capacitor (cp) = 15 pf for non-spread spectrum operation: for spread spectrum operation: vco gain (k vco ) = 900 mhz/v * 2 ? = ss_d3 (eq. 10) f in 4 * f mod ssvco = f vco f mod [0.5 * * (eq. 11) ( 1 + ss/400) + 5] resistor(rz) = (12.5 + 12.5*(rz[1] + 2*rz[2] + 4*rz[3])) * rz[0] + 6*(1 C rz[0]) kohms (eq. 12) resistor(rz) = (62.5 + 12.5*(rz[1] + 2*rz[2] + 4*rz[3])) * rz[0] + 6*(1 C rz[0]) kohms (eq. 13) charge pump (ip) = 24 * (1 + (2 * ip[0]) + (4 * ip[1]) + (8 * ip[2])) a (eq. 14) 3 + (5 * ip[3]) + (11 * ip[4]) charge pump (ip) = 12 * (1 + (2 * ip[0]) + (4 * ip[1]) + (8 * ip[2])) a (eq. 14) 27 + (5 * ip[3]) + (11 * ip[4])
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 11 idt5v49ee901 rev s 071015 pll loop bandwidth: charge pump gain (k ?? ) = ip / 2 ?? vco gain (k vco ) = 900 mhz/v * 2 ? m = total multiplier value (s ee the reference divider, feedback divider and output divider section for more detail) ? c = (rz * k ?? * k vco * cz)/(m * (cz + cp)) fc = ? c / 2 ?? note, the phase/frequency detector frequency (f pfd ) is typically seven times the pll closed-loop bandwidth (fc) but too high of a ratio will re duce the phase margin thus compromising loop stability. to determine if the loop is stable, the phase margin ( ? m) needs to be calculated as follows. phase margin: ? z = 1 / (rz * cz) ? p = (cz + cp)/(rz * cz * cp) ? m = (360 / 2 ? ) * [tan -1 ( ? c/ ? z) - tan -1 ( ? c/ ? p)] to ensure stability in the l oop, the phase margin is recommended to be > 60 but to o high will result in the lock time being excessively long. ce rtain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain lo op stability.
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 12 idt5v49ee901 rev s 071015 sel[2:0] function the idt5v49ee901 can support up to six unique configurations. users may pre-programmed all these configurations, and select the configurations using sel[2:0] pins. alternatively, users may use i 2 c interface to configure these registers on-the-fly. crystal/clock selection xtclksel bit is used to bypass a crystal oscillator circuit when external clock source is used. primsrc bit is used to select a primary clock from xin/ref and clkin. sd/oe pin function the polarity of the sd/oe signal pin can be programmed to be either active high or low with the sp bit (0x02). when sp is ?0? (default), the pin becomes active low and when sp is ?1?, the pin becomes active high. the sd/oe pin can be configured as either to shutdown the plls or to enable/disable the outputs configuration outx io standard users can configure the individual output io standard from a single 3.3v power supply. each output can support 3.3v lvttl. each output pair can support lvds, lvpecl or hcsl. out0 can only be 3.3v single-ended output. sel2 sel1 sel0 configur ation selections 0 0 0 select config0 0 0 1 select config1 0 1 0 select config2 0 1 1 select config3 1 0 0 select config4 1 0 1 select config5 1 1 0 reserved (do not use) 1 1 1 reserved (do not use) primsrc bit primary secondary 0x i n / r e f c l k i n 1 clkin xin/ref clksel input 01 clksel primsrc reference clock 0 0 xin/ref 01 c l k i n 10 c l k i n 1 1 xin/ref clock source primary clock source secondary clock source smx[1:0] swithcing mode primary to secondary secondary to primary 0x manual no no 10 auto yes no 11 auto-revertive yes yes outn os oe sp sd/oe input sh global shutdown truth table sh bit sp bit osn bit oen bit sd/oe outn 0 0 0 x x high-z 2 0 0 1 0 x enabled 0 0 1 1 0 enabled 0 0 1 1 1 suspended 0 1 0 x x high-z 2 0 1 1 0 x enabled 0 1 1 1 0 suspended 0 1 1 1 1 enabled 1 0 0 x 0 high-z 2 1 0 1 0 0 enabled 1 0 1 1 0 enabled 1 1 0 x 0 high-z 2 1 1 1 0 0 enabled 1 1 1 1 0 suspended 1x x x 1 suspended 1 note 1 : global shutdown note 2 : hi-z regardless of oem bits
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 13 idt5v49ee901 rev s 071015 programming the device i 2 c may be used to program the idt5v49ee901. ? device (slave) address = 7'b1101010 i 2 c programming the idt5v49ee901 is programmed through an i 2 c-bus serial interface, and is an i 2 c slave device. the read and write transfer formats are supported. the first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read. the frame formats are shown in the following illustration. framing each frame starts with a ?start condition? and ends with an ?end condition?. these are both generated by the master device. first byte transmitted on i 2 c bus 1 0 1 0 1 0 1 msb lsb r/w ack from slave r/w 0 ? slave will be written by master 1 ? slave will be read by master the first byte transmitted by the master is the slave address followed by the r/w bit. the slave acknowledges by sending a ?1? bit. 7-bit slave address
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 14 idt5v49ee901 rev s 071015 external i 2 c interface condition progwrite progwrite command frame writes can continue as long as a stop condition is not sent and each byte will increment the register address. progread note: if the expected read command is not from the next higher register to the previous read or write command, then set a known ?read? register address prior to a read operation by issuing the following command: prior to progread command set register address the user can ignore the stop condition above and use a repeated start condition instead, straight after the slave acknowledgement bit (i.e., followed by the progread command): progread command frame progsave note: progwrite is for writing to the idt5v49ee901 registers. progread is for reading the idt5v49ee901 registers. progsave is for saving all the contents of th e idt5v49ee901 registers to the eeprom. progrestore is for loading the entire eeprom contents to the idt5v49ee901 registers. saddress r/w ack command code ack register ack data ack p 7-bits 0 1-bit 8-bits: xxxx xx00 1-bit 8-bits 1-bit 8-bits 1-bit saddress r/w ack command code ack register ack p 7-bits 0 1-bit 8-bits: xxxx xx00 1-bit 8-bits 1-bit saddressr/w ack id byte ack data_1 ack data_2 ack data_last nack p 7-bits 1 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit saddress r/w ack command code ack p 7-bits 0 1-bit 8-bits: xxxx xx01 1-bit key: from master to slave from master to slave, but can be omitted if followed by the correct sequence normally, data transfer is terminated by a stop condition generated by the master. however, if the master still wishes to commu nicate on the bus, it can generate a separate start condition, and address another slave address without first generating a stop condition. from slave to master symbols: ack - acknowledge (sdat low) nack ? not acknowledge (sdat high) sr ? repeated start condition s ? start condition p ? stop condition
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 15 idt5v49ee901 rev s 071015 progrestore eeprom interface the idt5v49ee901 can also store its configuration in an internal eeprom. the contents of the device's internal programming registers can be saved to the eeprom by issuing a save instruction (progsave) and can be loaded back to the internal programming registers by issuing a restore instruction (progrestore). to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction executes after the stop condition is issued by the master, during which time the idt5v49ee901 will not generate acknowledge bits. the idt5 v49ee901 will acknowledge the instructions after it has completed execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the idt5v49ee901, an automatic restore is performed to load the eeprom contents into the internal programming registers. the idt5v49ee901 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. saddress r/w ack command code ack p 7-bits 0 1-bit 8-bits: xxxx xx10 1-bit
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 16 idt5v49ee901 rev s 071015 i 2 c bus dc characteristics i 2 c bus ac characterist ics for standard mode note 1: a device must internally provide a hold time of at least 300 ns for the sdat signal (referred t o the v ih (min) of the sclk signal) to bridge the undef ined region of the fa lling edge of sclk. symbol parameter conditions min typ max unit v ih input high level 0.7xv dd v v il input low level 0.3xv dd v v hys hysteresis of inputs 0.05xv dd v i in input leakage current 1.0 a v ol output low voltage i ol = 3 ma 0.4 v symbol parameter min typ max unit f sclk serial clock frequency (scl) 0 100 khz t buf bus free time between stop and start 4.7 s t su:start setup time, start 4.7 s t hd:start hold time, start 4 s t su:data setup time, data input (sda) 250 ns t hd:data hold time, data input (sda) 1 0 s t ovd output data valid from clock 3.45 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sdat, sclk) 1000 ns t f fall time, data and clock (sdat, sclk) 300 ns t high high time, clock (sclk) 4 s t low low time, clock (sclk) 4.7 s t su:stop setup time, stop 4 s
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 17 idt5v49ee901 rev s 071015 i 2 c bus ac characteri stics for fast mode note 1: a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to brid ge the undefined region of the falling edge of scl. symbol parameter min typ max unit f sclk serial clock frequency (scl) 0 400 khz t buf bus free time between stop and start 1.3 s t su:start setup time, start 0.6 s t hd:start hold time, start 0.6 s t su:data setup time, data input (sda) 100 ns t hd:data hold time, data input (sda) 1 0 s t ovd output data valid from clock 0.9 s c b capacitive load for each bus line 400 pf t r rise time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t f fall time, data and clock (sda, scl) 20 + 0.1xc b 300 ns t high high time, clock (scl) 0.6 s t low low time, clock (scl) 1.3 s t su:stop setup time, stop 0.6 s
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 18 idt5v49ee901 rev s 071015 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the idt5v49ee901. these rating s, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at th ese or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions symbol description min max unit v dd internal power supply voltage -0.5 +4.6 v v i input voltage 1 1.input negative and output voltage ratings may be exceeded if the input and output current ratings are observed. -0.5 +4.6 v v o output voltage (not to exceed 4.6 v) 1 -0.5 v dd +0.5 v t j junction temperature 150 c t stg storage temperature -65 150 c symbol parameter min typ max unit v dd power supply voltage for v dd pins supporting core and outputs 3.135 3.3 3.465 v v ddx power supply voltage for crystal oscillator. use filtered analog power supply if available. 3.135 3.3 3.465 v av dd analog power supply voltage. use filtered analog power supply if available. 3.135 3.3 3.465 v t a operating temperature, ambient -40 +85 c c load_out maximum load capacitance (3.3v lvttl only) 15 pf f in external reference crystal 8 50 mhz external reference clock clkin 1 200 t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 19 idt5v49ee901 rev s 071015 capacitance (t a = +25 c) dc electrical characteristics for 3.3-v lvttl 1 note 1: see ?recommended operating conditions? table. power supply characteristics for plls and lvttl outputs symbol parameter min typ max unit c in input capacitance (clkin, clksel, sd/oe, sda, scl, sel[2:0]) 37p f pull-down resistor clkin, clksel, sd/oe, sel[2:0] 180 k ? crystal specifications xtal_freq crystal frequency 8 50 mhz xtal_min minimum crystal load capacitance 3.5 pf xtal_max maximum crystal load capacitance 35.5 pf xtal_v pp voltage swing (peak-to-peak, nominal) 1.5 2.3 3.2 v symbol parameter test conditions min typ max unit v oh output high voltage 2.4 v dd v v ol output low voltage 0.4 v v ih input high voltage 2 v v il input low voltage 0.8 v i ozdd output leakage current 3-state outputs. v o = v dd or gnd, v dd = 3.6v 10 a supply current vs output frequency 0 20 40 60 80 100 120 140 0 25 50 75 100 125 150 175 200 output frequency(mhz) supply current(ma) no outputs ref output on 2 outputs on 3 outputs on 4 outputs on 6 outputs on 8 outputs on 9 outputs on total supply current vs pll frequency 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 pll frequency(mhz) total supply current(ma) pll0 on idd(ma) pll0+pll1 on idd(ma) pll0+pll1+pll2 on idd(ma) all plls on idd(ma)
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 20 idt5v49ee901 rev s 071015 dc electrical characteristics for lvds power supply characteri stics for lvds outputs 1 note 1: output banks 4 and 5 are toggling. other output banks are powered down. note 2: the termination resistors are excluded from these measurements. dc electrical characteristics for lvpecl power supply characteri stics for lvpecl outputs 1 symbol parameter min typ max unit v ot (+) differential output voltage fo r the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v dd 92 4m a i osd differential outputs shor t circuit current, v out + = v out -6 1 2 m a symbol parameter test conditions 2 typ max unit i ddq quiescent v dd power supply current ref = low outputs enabled, all outputs unloaded 68 90 ma i ddd dynamic v dd power supply current per output v dd = max., c l = 0pf 30 45 a/mhz i tot to t a l po w e r v dd supply current f reference clock = 100 mhz, c l = 2 pf 86 130 ma f reference clock = 200 mhz, c l = 2 pf 100 150 f reference clock = 400 mhz, c l = 2 pf 122 190 symbol parameter min typ max unit v oh output voltage high, terminated through 50 ? tied to v dd -2 v v dd -1.2 v dd -0.9 v v ol output voltage low, terminated through 50 ? tied to v dd -2 v v dd -1.95 v dd -1.61 v v swing peak-to-peak output voltage swing 0.55 0.93 v symbol parameter test conditions 2 typ max unit i ddq quiescent v dd power supply current ref = low outputs enabled, all outputs unloaded 86 110 ma i ddd dynamic v dd power supply current per output v dd = max., c l = 0pf 35 50 a/mhz
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 21 idt5v49ee901 rev s 071015 note 1: output banks 4 and 5 are toggling. other output banks are powered down. note 2: the termination resistors are excluded from these measurements. dc electrical characteristics for hcsl power supply characteristics for hcsl outputs 1 note 1: output banks 4 and 5 are toggling. other output banks are powered down. note 2: the termination resistors are excluded from these measurements. i tot to t a l po w e r v dd supply current f reference clock = 100 mhz, c l = 2 pf 120 180 ma f reference clock = 200 mhz, c l = 2 pf 130 190 f reference clock = 400 mhz, c l = 2 pf 140 210 symbol parameter min typ max unit v oh output voltage high 660 700 850 mv v ol output voltage low -150 0 27 mv crossing point voltage absolute 250 350 550 mv symbol parameter test conditions 2 typ max unit i ddq quiescent v dd power supply current ref = low outputs enabled, all outputs unloaded 68 90 ma i ddd dynamic v dd power supply current per output v dd = max., c l = 0pf 30 45 a/mhz i tot to t a l po w e r v dd supply current f reference clock = 100 mhz, c l = 2 pf 86 130 ma f reference clock = 200 mhz, c l = 2 pf 100 150 f reference clock = 400 mhz, c l = 2 pf 122 190 symbol parameter test conditions 2 typ max unit
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 22 idt5v49ee901 rev s 071015 ac timing electrical characteristics (spread spectrum generation = off) symbol parameter test conditions min. typ. max. units f in 1 input frequency input frequency limit (clkin) 1 200 mhz input frequency limit (xin/ref) 8 100 mhz 1 / t1 output frequency single ended clock output limit (lvttl) 0.001 200 mhz differential clock output limit (lvpecl/ lvds/hcsl) 0.001 500 f vco vco frequency vco operating frequency range 100 1300 mhz f pfd pfd frequency pfd operating frequency range 0.5 1 100 mhz f bw loop bandwidth based on loop filter resistor and capacitor values 0.01 10 mhz t2 input duty cycle duty cycle for input 40 60 % t3 output duty cycle measured at v dd /2, all outputs except reference output 45 55 % measured at v dd /2, reference output 40 60 % t4 2 slew rate, slew[1:0] = 00 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of v dd (output load = 5 pf) 3.5 v/ns slew rate, slew[1:0] = 01 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of v dd (output load = 5 pf) 2.75 slew rate, slew[1:0] = 10 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of v dd (output load = 5 pf) 2 slew rate, slew[1:0] = 11 single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of v dd (output load = 5 pf) 1.25 t5 rise times lvds, 20% to 80% 600 ps fall times lvds, 80% to 20% 600 rise times lvpecl, 20% to 80% 600 ps fall times lvpecl, 80% to 20% 600 rise times hcsl, from 0.175 v to 0.525 v 175 400 700 ps fall times hcsl, from 0.525 v to 0.175 v 175 400 700
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 23 idt5v49ee901 rev s 071015 spread spectrum genera tion specifications test circuits and conditions test circuits for dc outputs t7 clock jitter 6 peak-to-peak period jitter, 1pll, multiple output frequencies swit ching, lvttl outputs 80 100 ps peak-to-peak period jitter, all 4 plls on, lvttl outputs 3 200 270 ps peak-to-peak period jitter, 1pll, multiple output frequencies switching, lvpecl, lvds or hcsl outputs 60 80 ps peak-to-peak period jitter, all 4 plls on, lvpecl, lvds or hcsl outputs 120 160 ps t8 output skew skew between output to output on the same bank 75 ps t9 4 lock time pll lock time from power-up 10 20 ms t10 5 lock time pll lock time from shutdown mode 2 ms 1.practical lower frequency is determined by loop filter settings. 2.a slew rate of 2.75v/ns or greater should be selected for output frequencies of 100mhz or higher. 3.jitter measured with clock outputs of 27 mhz, 48 mhz, 24.576 mhz, 74.25 mhz and 25 mhz. 4.includes loading the configuration bits from eeprom to p ll registers. it does not include eeprom programming/write time. 5.actual pll lock time depends on the loop configuration. 6. not guaranteed until customer spec ific configuration is approved by idt. symbol parameter description min typ max unit f in 1 1.practical lower frequency is determined by loop filter settings. 2. not guaranteed until customer spec ific configuration is approved by idt. input frequency input frequency limit 1 400 mhz f mod mod frequency modulation frequency 33 120 khz f spread 2 spread value amount of spread value (programmable) - down spread -0.5 -4.0 %f out amount of spread value (programmable) - center spread 0.25 2.0 symbol parameter test conditions min. typ. max. units outx v dd clk out gnd c l 0.1f v ddox 0.1f
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 24 idt5v49ee901 rev s 071015 other termination scheme (block diagram) outx clk out gnd outx gnd outx gnd v dd -2v v dd -2v clk out clk out clk out 2 pf clk out outx gnd gnd clk out 49.9 ohm clk out 33 ohm 2 pf 2 pf 2 pf 5 pf 49.9 ohm 49.9 ohm 49.9 ohm 33 ohm 2 pf 2 pf lvttl: 5 pf for each output lv d s : 1 0 0 ? between differential outputs lvpecl hcsl
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 25 idt5v49ee901 rev s 071015 programming registers table addr default register hex value bit # description 7654321 0 0x00 00 reserved hw/sw hardware/software mode control hw/sw - 0=hw, 1=sw 0x01 00 reserved sel[2:0] sel[2:0] - selects configuration in sw mode 0x02 02 sp oe6 oe5 oe4 oe3 oe2 oe1 oe0 oex=output power suspend function for outx (?1?=outx will be suspended on sd/oe pin. disable mode is defined by oemx bits), ?0?=outputs enabled and no association with oe pin (default). 0x03 02 reserved os*[6:0] os*[6:0] - output suspend, active low. overwrites oe setting. 0x04 0f sh reserved plls*[3:0] plls*[3:0] - pll suspend, active low sh - shutdown/oe configuration 0x05 04 reserved xtclksel reserved xtclksel - crystal/clock select. 0=crytal, 1=iclk 0x06 00 reserved 0x07 00 reserved xtal[4:0] xtal[4:0] - crystal cap 0x08 00 reserved 0x09 00 reserved 0x0a 10 cz0_cfg4 ip0[2:0]_cfg4 rz0[3:0]_cfg4 pll0 loop parameter 0x0b 10 cz0_cfg5 ip0[2:0]_cfg5 rz0[3:0]_cfg5 0x0c 10 cz0_cfg0 ip0[2:0]_cfg0 rz0[3:0]_cfg0 0x0d 10 cz0_cfg1 ip0[2:0]_cfg1 rz0[3:0]_cfg1 0x0e 10 cz0_cfg2 ip0[2:0]_cfg2 rz0[3:0]_cfg2 0x0f 10 cz0_cfg3 ip0[2:0]_cfg3 rz0[3:0]_cfg3 0x10 00 reserved d0[6:0]_cfg0 pll0 input divider and input sel d0[6:0] - 127 step ref div d0 = 0 means power down. 0x11 00 reserved d0[6:0]_cfg1 0x12 00 reserved d0[6:0]_cfg2 0x13 00 reserved d0[6:0]_cfg3 0x14 00 reserved d0[6:0]_cfg4 0x15 00 reserved d0[6:0]_cfg5 0x16 01 n0[7:0]_cfg4 n - feedback divider 2 - 4095 (values of ?0? and ?1? are not allowed) total feedback with a, using provided calculation 0x17 01 n0[7:0]_cfg5 0x18 01 n0[7:0]_cfg0 0x19 01 n0[7:0]_cfg1 0x1a 01 n0[7:0]_cfg2 0x1b 01 n0[7:0]_cfg3 0x1c 00 a0[3:0]_cfg0 n0[11:8]_cfg0 0x1d 00 a0[3:0]_cfg1 n0[11:8]_cfg1 0x1e 00 a0[3:0]_cfg2 n0[11:8]_cfg2 0x1f 00 a0[3:0]_cfg3 n0[11:8]_cfg3 0x20 00 a0[3:0]_cfg4 n0[11:8]_cfg4 0x21 00 a0[3:0]_cfg5 n0[11:8]_cfg5 0x22 10 cz1_cfg4 ip1[2:0]_cfg4 rz1[3:0]_cfg4 pll1 loop parameter 0x23 10 cz1_cfg5 ip1[2:0]_cfg5 rz1[3:0]_cfg5 0x24 10 cz1_cfg0 ip1[2:0]_cfg0 rz1[3:0]_cfg0 0x25 10 cz1_cfg1 ip1[2:0]_cfg1 rz1[3:0]_cfg1 0x26 10 cz1_cfg2 ip1[2:0]_cfg2 rz1[3:0]_cfg2 0x27 10 cz1_cfg3 ip1[2:0]_cfg3 rz1[3:0]_cfg3
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 26 idt5v49ee901 rev s 071015 0x28 00 reserved d1[6:0]_cfg0 pll1 input divider and input sel d1[6:0] - 127 step ref div d1 = 0 means power down. 0x29 00 reserved d1[6:0]_cfg1 0x2a 00 reserved d1[6:0]_cfg2 0x2b 00 reserved d1[6:0]_cfg3 0x2c 00 reserved d1[6:0]_cfg4 0x2d 00 reserved d1[6:0]_cfg5 0x2e 01 n1[7:0]_cfg4 n - feedback divider 2 - 4095 (value of ?0? is not allowed) total feedback with a, using provided calculation 0x2f 01 n1[7:0]_cfg5 0x30 01 n1[7:0]_cfg0 0x31 01 n1[7:0]_cfg1 0x32 01 n1[7:0]_cfg2 0x33 01 n1[7:0]_cfg3 0x34 00 n3[11:8]_cfg0 n1[11:8]_cfg0 pll3 feedback divider 0x35 00 n3[11:8]_cfg1 n1[11:8]_cfg1 0x36 00 n3[11:8]_cfg2 n1[11:8]_cfg2 0x37 00 n3[11:8]_cfg3 n1[11:8]_cfg3 0x38 00 n3[11:8]_cfg4 n1[11:8]_cfg4 0x39 00 n3[11:8]_cfg5 n1[11:8]_cfg5 0x3a 00 cz2_cfg4 ip2[2:0]_cfg4 rz2[3:0]_cfg4 pll2 loop parameter 0x3b 00 cz2_cfg5 ip2[2:0]_cfg5 rz2[3:0]_cfg5 0x3c 00 cz2_cfg0 ip2[2:0]_cfg0 rz2[3:0]_cfg0 0x3d 00 cz2_cfg1 ip2[2:0]_cfg1 rz2[3:0]_cfg1 0x3e 00 cz2_cfg2 ip2[2:0]_cfg2 rz2[3:0]_cfg2 0x3f 00 cz2_cfg3 ip2[2:0]_cfg3 rz2[3:0]_cfg3 0x40 00 reserved d2[6:0]_cfg0 pll2 reference divide and input select d2[6:0] - 127 step ref div d2 = 0 means power down. 0x41 00 reserved d2[6:0]_cfg1 0x42 00 reserved d2[6:0]_cfg2 0x43 00 reserved d2[6:0]_cfg3 0x44 00 reserved d2[6:0]_cfg4 0x45 00 reserved d2[6:0]_cfg5 0x46 01 n2[7:0]_cfg4 n2[7:0] - pll2 feedback divider 2 - 4095 (value of ?0? is not allowed). (see addr 0x4c:0x51 for n2[15:8]) 0x47 01 n2[7:0]_cfg5 0x48 01 n2[7:0]_cfg0 0x49 01 n2[7:0]_cfg1 0x4a 01 n2[7:0]_cfg2 0x4b 01 n2[7:0]_cfg3 0x4c 80 ssenb_cfg0 0 0 ip3[4]_cfg0 n2[11:8]_cfg0 n2[11:8] - pll2 feedback divide pll3 spread spectrum ssenb - spread spectrum enable ssenb = 1 means on ip3[4:0] - pll3 charge pump current. 0x4d 80 ssenb_cfg1 0 0 ip3[4]_cfg1 n2[11:8]_cfg1 0x4e 80 ssenb_cfg2 0 0 ip3[4]_cfg2 n2[11:8]_cfg2 0x4f 80 ssenb_cfg3 0 0 ip3[4]_cfg3 n2[11:8]_cfg3 0x50 80 ssenb_cfg4 0 0 ip3[4]_cfg4 n2[11:8]_cfg4 0x51 80 ssenb_cfg5 0 0 ip3[4]_cfg5 n2[11:8]_cfg5 0x52 xx 1 reserved 0x53 xx 1 reserved 0x54 xx 1 reserved 0x55 xx 1 reserved addr default register hex value bit # description 7654321 0
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 27 idt5v49ee901 rev s 071015 0x56 00 ip3[3:0]_cfg4 rz3[3:0]_cfg4 pll3 loop parameter 0x57 00 ip3[3:0]_cfg5 rz3[3:0]_cfg5 0x58 00 ip3[3:0]_cfg0 rz3[3:0]_cfg0 0x59 00 ip3[3:0]_cfg1 rz3[3:0]_cfg1 0x5a 00 ip3[3:0]_cfg2 rz3[3:0]_cfg2 0x5b 00 ip3[3:0]_cfg3 rz3[3:0]_cfg3 0x5c 03 reserved d3[6:0]_cfg0 pll3 reference divide and input sel d3[6:0] - 127 step ref div d3 = 0 means power down. 0x5d 03 reserved d3[6:0]_cfg1 0x5e 03 reserved d3[6:0]_cfg2 0x5f 03 reserved d3[6:0]_cfg3 0x60 03 reserved d3[6:0]_cfg4 0x61 03 reserved d3[6:0]_cfg5 0x62 0c n3[7:0]_cfg4 n - feedback divider 12 - 4095 (values of ?0? through ?11? are not allowed) 0x63 0c n3[7:0]_cfg5 0x64 0c n3[7:0]_cfg0 0x65 0c n3[7:0]_cfg1 0x66 0c n3[7:0]_cfg2 0x67 0c n3[7:0]_cfg3 0x68 00 ssvco[7:0]_cfg0 ssvco[7:0] - pll3 spread spectrum loop feedback counter see addr 0x80:0x85 for ssvco[15:8] 0x69 00 ssvco[7:0]_cfg1 0x6a 00 ssvco[7:0]_cfg2 0x6b 00 ssvco[7:0]_cfg3 0x6c 00 ssvco[7:0]_cfg4 0x6d 00 ssvco[7:0]_cfg5 0x6e 00 ss_d3[7:0]_cfg4 ss_d[7:0] - pll3 spread spectrum reference divide 0x6f 00 ss_d3[7:0]_cfg5 0x70 00 ss_d3[7:0]_cfg0 0x71 00 ss_d3[7:0]_cfg1 0x72 00 ss_d3[7:0]_cfg2 0x73 00 ss_d3[7:0]_cfg3 0x74 01 reserved reserved 0x75 03 oem0[1:0] slew0[1:0] inv0 reserved s1 s3 output controls s1=1 - out1/out2 are from div1/div2 respectively s1=0 - both from div2 s3 =1 - out3/out6 are from div3/div6 s3=0 - both from div6 slew# - lvttl only oem#?output enable mode x0 - tristated 01 - park low 11 - park high oem0 controls out0 only 0x76 00 oem1[1:0] slew1[1:0] inv1[1:0] lvl1[1:0] output controls lvl1[1:0] - output pair out1/out2 [00] - lvttl [01] - lvds [10] - lvpecl [11] - hcsl inv1 [clk1, clk2] [0] - normal [1] - invert clock oem1 controls out1/out2 addr default register hex value bit # description 7654321 0
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 28 idt5v49ee901 rev s 071015 0x77 00 slew2[1:0] cmen3 cmen1 cmen# - common mode enable set to 1 for lvds set to 0 for lvttl, lvpecl, hcsl 0x78 00 oem3[1:0] slew3[1:0] inv3[1:0] lvl3[1:0] oem3 controls out3 and out6 0x79 00 oem4[1:0] slew4[1:0] inv4[1:0] lvl4[1:0] oem4 controls out4 and out4b 0x7a 00 oem5[1:0] slew5[1:0] inv5[1:0] lvl5[1:0] oem5 controls out5 and out5b 0x7b 00 slew6[1:0] cmen5 cmen4 0x7c xx 1 reserved 0x7d xx 1 reserved 0x7e xx 1 reserved 0x7f xx 1 reserved 0x80 00 ssvco[15:8]_cfg0 pll3 spread spectrum feedback counter 0x81 00 ssvco[15:8]_cfg1 0x82 00 ssvco[15:8]_cfg2 0x83 00 ssvco[15:8]_cfg3 0x84 00 ssvco[15:8]_cfg4 0x85 00 ssvco[15:8]_cfg5 0x86 00 reserved 0x87 00 reserved addr default register hex value bit # description 7654321 0
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 29 idt5v49ee901 rev s 071015 0x88 ff pm1_cfg0 q1[6:0]_cfg0 output divides for q<>111111, pm=0 - divide by 2 pm=1, (q+2)*2 for q=1111111 pm=0, disable the output divider pm=1, bypass the output divide, (divide by 1) 0x89 ff pm1_cfg1 q1[6:0]_cfg1 0x8a ff pm1_cfg2 q1[6:0]_cfg2 0x8b ff pm1_cfg3 q1[6:0]_cfg3 0x8c ff pm1_cfg4 q1[6:0]_cfg4 0x8d ff pm1_cfg5 q1[6:0]_cfg5 0x8e 7f pm2_cfg4 q2[6:0]_cfg4 0x8f 7f pm2_cfg5 q2[6:0]_cfg5 0x90 7f pm2_cfg0 q2[6:0]_cfg0 0x91 7f pm2_cfg1 q2[6:0]_cfg1 0x92 7f pm2_cfg2 q2[6:0]_cfg2 0x93 7f pm2_cfg3 q2[6:0]_cfg3 0x94 7f pm3_cfg0 q3[6:0]_cfg0 0x95 7f pm3_cfg1 q3[6:0]_cfg1 0x96 7f pm3_cfg2 q3[6:0]_cfg2 0x97 7f pm3_cfg3 q3[6:0]_cfg3 0x98 7f pm3_cfg4 q3[6:0]_cfg4 0x99 7f pm3_cfg5 q3[6:0]_cfg5 0x9a 7f pm4_cfg4 q4[6:0]_cfg4 0x9b 7f pm4_cfg5 q4[6:0]_cfg5 0x9c 7f pm4_cfg0 q4[6:0]_cfg0 0x9d 7f pm4_cfg1 q4[6:0]_cfg1 0x9e 7f pm4_cfg2 q4[6:0]_cfg2 0x9f 7f pm4_cfg3 q4[6:0]_cfg3 0xa0 7f pm5_cfg0 q5[6:0]_cfg0 0xa1 7f pm5_cfg1 q5[6:0]_cfg1 0xa2 7f pm5_cfg2 q5[6:0]_cfg2 0xa3 7f pm5_cfg3 q5[6:0]_cfg3 0xa4 7f pm5_cfg4 q5[6:0]_cfg4 0xa5 7f pm5_cfg5 q5[6:0]_cfg5 0xa6 7f pm6_cfg4 q6[6:0]_cfg4 0xa7 7f pm6_cfg5 q6[6:0]_cfg5 0xa8 7f pm6_cfg0 q6[6:0]_cfg0 0xa9 7f pm6_cfg1 q6[6:0]_cfg1 0xaa 7f pm6_cfg2 q6[6:0]_cfg2 0xab 7f pm6_cfg3 q6[6:0]_cfg3 0xac 00 tssc[3:0]_cfg0 nssc[3:0]_cfg0 pll0 spread spectrum control 0xad 00 tssc[3:0]_cfg1 nssc[3:0]_cfg1 0xae 00 tssc[3:0]_cfg2 nssc[3:0]_cfg2 0xaf 00 tssc[3:0]_cfg3 nssc[3:0]_cfg3 0xb0 00 tssc[3:0]_cfg4 nssc[3:0]_cfg4 0xb1 00 tssc[3:0]_cfg5 nssc[3:0]_cfg5 0xb2 00 dith_cfg4 x2_cfg4 ssoffset[5:0]_cfg4 0xb3 00 dith_cfg5 x2_cfg5 ssoffset[5:0]_cfg5 0xb4 00 dith_cfg0 x2_cfg0 ssoffset[5:0]_cfg0 0xb5 00 dith_cfg1 x2_cfg1 ssoffset[5:0]_cfg1 0xb6 00 dith_cfg2 x2_cfg2 ssoffset[5:0]_cfg2 0xb7 00 dith_cfg3 x2_cfg3 ssoffset[5:0]_cfg3 0xb8 11 sd1[3:0]_cfg0 sd0[3:0]_cfg0 0xb9 11 sd1[3:0]_cfg1 sd0[3:0]_cfg1 0xba 11 sd1[3:0]_cfg2 sd0[3:0]_cfg2 addr default register hex value bit # description 7654321 0
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 30 idt5v49ee901 rev s 071015 1 . memory bytes do not exist. readback will be last value in shift register. if read ing sequentially, value in 0x51 will be returned. 0xbb 11 sd1[3:0]_cfg3 sd0[3:0]_cfg3 0xbc 11 sd1[3:0]_cfg4 sd0[3:0]_cfg4 0xbd 11 sd1[3:0]_cfg5 sd0[3:0]_cfg5 0xbe ae src1[1:0]_cfg4 src0[1:0]_cfg4 pdpl3_cfg4 sm[1:0]_cfg4 primsrc_cfg4 output divide source selection 0xbf ae src1[1:0]_cfg5 src0[1:0]_cfg5 pdpl3_cfg5 sm[1:0]_cfg5 primsrc_cfg5 primsrc - primary source - crystal or iclock 0 = crystal/refin 1 = clkin 0xc0 ae src1[1:0]_cfg0 src0[1:0]_cfg0 pdpl3_cfg0 sm[1:0]_cfg0 primsrc_cfg0 sm = switch mode 0x = manual 10 = reserved 11 = auto-revertive 0xc1 ae src1[1:0]_cfg1 src0[1:0]_cfg1 pdpl3_cfg1 sm[1:0]_cfg1 primsrc_cfg1 pdpl3 - pll3 shutdown 0 = normal 1 = shut down 0xc2 ae src1[1:0]_cfg2 src0[1:0]_cfg2 pdpl3_cfg2 sm[1:0]_cfg2 primsrc_cfg2 src = mux control bit prior to div# src0[1:0] 00 - div1 01 - div3 10 - reference input 0xc3 ae src1[1:0]_cfg3 src0[1:0]_cfg3 pdpl3_cfg3 sm[1:0]_cfg3 primsrc_cfg3 0xc4 24 src4[0]_cfg0 src3[2:0]_cfg0 src2[2:0]_cfg0 src1[2]_cfg0 src1/src2/src3..src5 000 - div1 001 - div3 010 - reference input 011 - reserved 100 - pll0 101 - pll1 110 - pll2 111 - pll3 0xc5 24 src4[0]_cfg1 src3[2:0]_cfg1 src2[2:0]_cfg1 src1[2]_cfg1 0xc6 24 src4[0]_cfg2 src3[2:0]_cfg2 src2[2:0]_cfg2 src1[2]_cfg2 0xc7 24 src4[0]_cfg3 src3[2:0]_cfg3 src2[2:0]_cfg3 src1[2]_cfg3 0xc8 24 src4[0]_cfg4 src3[2:0]_cfg4 src2[2:0]_cfg4 src1[2]_cfg4 0xc9 24 src4[0]_cfg5 src3[2:0]_cfg5 src2[2:0]_cfg5 src1[2]_cfg5 0xca 49 src6[2:0]_cfg4 src5[2:0]_cfg4 src4[2:1]_cfg4 src6 000 - reserved 001 - reserved 010 - reference input 011 - reserved 100 - reserved 101 - pll1 110 - reserved 111 - reserved quiet mux 0xcb 49 src6[2:0]_cfg5 src5[2:0]_cfg5 src4[2:1]_cfg5 0xcc 49 src6[2:0]_cfg0 src5[2:0]_cfg0 src4[2:1]_cfg0 0xcd 49 src6[2:0]_cfg1 src5[2:0]_cfg1 src4[2:1]_cfg1 0xce 49 src6[2:0]_cfg2 src5[2:0]_cfg2 src4[2:1]_cfg2 0xcf 49 src6[2:0]_cfg3 src5[2:0]_cfg3 src4[2:1]_cfg3 addr default register hex value bit # description 7654321 0
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 31 idt5v49ee901 rev s 071015 marking diagram (nlg32) marking diagram (pgg28) notes: 1. ?#? is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?$? is the assembly mark code. 4. ?g? after the two-letter package code designates rohs compliant package. 5. ?i? at the end of part number indicates industrial temperature range. 6. bottom marking: country of origin if not usa. thermal characteristics 28-pin tssop thermal characteristics 32-pin vfqfpn idt5v49ee901 nlgi #yyww$ 1 14 15 28 idt5v49ee901pggi #yyww$ parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 83 ? c/w ? ja 1 m/s air flow 75 ? c/w ? ja 3 m/s air flow 61 ? c/w thermal resistance junction to case ? jc 60 ? c/w thermal resistance junction to top of case ? jt still air 4.5 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 34 ? c/w ? ja 1 m/s air flow 29 ? c/w ? ja 3 m/s air flow 27 ? c/w thermal resistance junction to case ? jc 32 ? c/w
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 32 idt5v49ee901 rev s 071015 32-pin qfn landing pattern x d2 y ad zd e2 ae ze gd ge x d2 y ad zd e2 ae ze gd ge 0.28 x(max) 0.69 yr ef 3.93 g( min) 3.78 a(max) 3.63 e2/ d2(max) 5.31 z( max) dimensions 0.28 x(max) 0.69 yr ef 3.93 g( min) 3.78 a(max) 3.63 e2/ d2(max) 5.31 z( max) dimensions unit : m m
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 33 idt5v49ee901 rev s 071015 package outline and package dimensions (28-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95, mo-153 index area 1 2 28 d e1 e seating plane a1 a a2 e - c - b aaa c ? c l millimeters inches symbol min max min max a- - 1 . 2 0 - - 0 . 0 4 7 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 9.60 9.80 0.378 0.386 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 ? 0 ? 8 ? 0 ? 8 ? aaa -- 0.10 -- 0.004
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 34 idt5v49ee901 rev s 071015 package outline and package dimensions (32-pin vfqfpn, 0.50mm pitch) package dimensions are kept current with jedec publication no. 95 ordering information ?g? after the two-letter package code are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 5v49ee901pggi see page 31 tubes 28pin tssop -40 to +85 ? c 5v49ee901pggi8 see page 31 tape and reel 28pin tssop -40 to +85 ? c 5V49EE901NLGI see page 31 trays 32pin vfqfpn -40 to +85 ? c 5V49EE901NLGI8 see page 31 tape and reel 32pin vfqfpn -40 to +85 ? c thermal base ep ? exposed thermal pad should be externally connected to gnd
idt5v49ee901 eeprom programmable clock ge nerator clock synthesizer idt? eeprom programmable clock generator 35 idt5v49ee901 rev s 071015 revision history rev. originator date description of change a r.willner 4/22/09 advance information. b r.willner 5/04/09 identified vddx (crystal oscillator power) and avdd (analog power) on device. c r.willner 6/04/09 add default configurations, pull-down resistor values on input pins. released datasheet from advanced information. d r.willner 06/10/09 updates: crystal load specs; ?output duty cycle? specs; addresses 0x07, 0x02 and 0xbf in ?programming registers? table. e r.willner 7/21/09 corrected 32vfqfpn marking to be consistant with manufacturing. f r.willner 08/26/09 updated 32-pin vfqfpn thermal data g r.willner 10/05/09 changed ip3[3: 0] to ip3[4:0] ; updated ?programming registers table?. h r.willner 12/07/09 updated vdd min/max sp ecs in recommended operation conditions i r.willner 12/09/09 increased max vco frequency to 1300 mhz. j r.willner 02/23/10 updated recommen ded operation conditions to include vddx and avdd parameters. k r.willner 04/22/11 added landing pattern diagram for 32qfn. l a. tsui 07/07/11 updated package dimension drawing m r. willner 12/6/11 correct pin description. n r. willner 04/17/12 1. change description for sdat and sclk pins. 2. add new footnotes to pin descriptions table 3. added section "crystal clock selection" 4. added logic diagram and truth tabl e for "sd/oe pin function" section. 5. corrected register readback va lues for 0x52~0x54 and 0x7c~0x7f. 6. update to qfn package drawing - exposed thermal pad callout. p a. tsui 06/01/12 1. updated sd-oe pin description; from (default is active high) to (default is active low) 2. updated ?outn? column in truth tabl e with ?high-z? specs and added footnote 2, ?high-z regardless of oem bits?. 3. updated ?sd-oe pin function? section to reflect that sp is ?0?changed from active high to active low, and sp is ?1? changed from active low to active high. q r.willner 06/18/12 added min/max spread values to "spread spectrum generation specifications" table; fmod - max. 120khz; down spread - min. -0 .5%, max. -4.0%; center spread - min. 0.25%, max. 2.0% r r.willner 09/24/12 change differential ou tputs from 5pf loads to 2pf loads so that they are consistent with the industry. capacitive loads were also added to the test circuit diagrams for hcsl outputs. slew rate (t4) output load test conditions were also changed from 15pf to 5pf. s 07/10/15 a.b. added the following note under ac timing electrical characteristics table: ?not guaranteed until customer specific configuration is approved by idt.?
? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without no tice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all ot her brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: w w w.i dt.c om idt5v49ee901 eeprom programmable clock generator clock synthesizer

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